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| author | Nathan Binkert <nate@binkert.org> | 2008-06-18 10:15:21 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2008-06-18 10:15:21 -0700 |
| commit | 67a33eed40f0a551fdf9bf1059928cda1c2d7fdb (patch) | |
| tree | 0b7cc05da8cf12189d998b8e67a729a21cc919b5 /src/cpu/simple/AtomicSimpleCPU.py | |
| parent | f24f2c57b6cd8dd45681c08d1ddfbd40a2914987 (diff) | |
| download | gem5-67a33eed40f0a551fdf9bf1059928cda1c2d7fdb.tar.xz | |
AtomicSimpleCPU: Separate data stalls from instruction stalls.
Separate simulation of icache stalls and dat stalls.
Diffstat (limited to 'src/cpu/simple/AtomicSimpleCPU.py')
| -rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 28c2aa9c9..a0b358439 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -33,7 +33,8 @@ from BaseCPU import BaseCPU class AtomicSimpleCPU(BaseCPU): type = 'AtomicSimpleCPU' width = Param.Int(1, "CPU width") - simulate_stalls = Param.Bool(False, "Simulate cache stall cycles") + simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") + simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") if build_env['FULL_SYSTEM']: |