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authorDam Sunwoo <dam.sunwoo@arm.com>2014-09-20 17:17:43 -0400
committerDam Sunwoo <dam.sunwoo@arm.com>2014-09-20 17:17:43 -0400
commitca3513d63038e562782cd193c00c3892a276bb5d (patch)
treec8f92b165105989fdb9b9b75d594880157da541f /src/cpu/simple/AtomicSimpleCPU.py
parent7329c0e20ba2c78f57dd53e90246ccbe3efa158d (diff)
downloadgem5-ca3513d63038e562782cd193c00c3892a276bb5d.tar.xz
cpu: use probes infrastructure to do simpoint profiling
Instead of having code embedded in cpu model to do simpoint profiling use the probes infrastructure to do it.
Diffstat (limited to 'src/cpu/simple/AtomicSimpleCPU.py')
-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 7a066457d..04592c68a 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -40,6 +40,7 @@
from m5.params import *
from BaseSimpleCPU import BaseSimpleCPU
+from SimPoint import SimPoint
class AtomicSimpleCPU(BaseSimpleCPU):
"""Simple CPU model executing a configurable number of
@@ -61,6 +62,8 @@ class AtomicSimpleCPU(BaseSimpleCPU):
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
fastmem = Param.Bool(False, "Access memory directly")
- simpoint_profile = Param.Bool(False, "Generate SimPoint BBVs")
- simpoint_interval = Param.UInt64(100000000, "SimPoint Interval Size (insts)")
- simpoint_profile_file = Param.String("simpoint.bb.gz", "SimPoint BBV file")
+
+ def addSimPointProbe(self, interval):
+ simpoint = SimPoint()
+ simpoint.interval = interval
+ self.probeListener = simpoint