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authorGabe Black <gblack@eecs.umich.edu>2011-02-03 20:23:00 -0800
committerGabe Black <gblack@eecs.umich.edu>2011-02-03 20:23:00 -0800
commit00f24ae92c7b9aa73e12fd8160b5756e80126db2 (patch)
tree1d149846db0efdc77c635891c6c1433d3af1817d /src/cpu/simple/TimingSimpleCPU.py
parent869a046e413d7cbfdda4e33eed8191004017a83f (diff)
downloadgem5-00f24ae92c7b9aa73e12fd8160b5756e80126db2.tar.xz
Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.
Diffstat (limited to 'src/cpu/simple/TimingSimpleCPU.py')
-rw-r--r--src/cpu/simple/TimingSimpleCPU.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 6b83c41aa..8d6888f72 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -33,4 +33,4 @@ class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
- _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
+ _cached_ports = BaseSimpleCPU._cached_ports + ['icache_port', 'dcache_port']