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| author | Korey Sewell <ksewell@umich.edu> | 2007-11-15 00:14:20 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2007-11-15 00:14:20 -0500 |
| commit | 375ddf8d25c3d81a77bd5dd7b70f84a0dbe48fe8 (patch) | |
| tree | 525cf56502718b69fb7f0e78162a8d5e63256489 /src/cpu/simple/TimingSimpleCPU.py | |
| parent | 2820a448e2bcb861d099b1256087004462b78895 (diff) | |
| parent | 7c8e4ca3a3b66becbc3e4e7b5e106f5c44b09b6f (diff) | |
| download | gem5-375ddf8d25c3d81a77bd5dd7b70f84a0dbe48fe8.tar.xz | |
branch merge
--HG--
extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
Diffstat (limited to 'src/cpu/simple/TimingSimpleCPU.py')
| -rw-r--r-- | src/cpu/simple/TimingSimpleCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 2fcde175c..7e777e813 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -38,4 +38,4 @@ class TimingSimpleCPU(BaseCPU): profile = Param.Latency('0ns', "trace the kernel stack") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] + _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port'] |