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authorRichard Strong <rstrong@hp.com>2008-08-18 10:50:58 -0700
committerRichard Strong <rstrong@hp.com>2008-08-18 10:50:58 -0700
commit8d018aef0f9de7129a77172a4164f36b2b093be6 (patch)
treeff3d46df0e6c495ab95454e69607993ff45fe14f /src/cpu/simple/TimingSimpleCPU.py
parent6248e12704275bf4cc88f1743bb3a4bff7adcf9f (diff)
downloadgem5-8d018aef0f9de7129a77172a4164f36b2b093be6.tar.xz
Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused problems for intialization of the interval value. If a child class's profile value was defined, the parent BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the multiple redifitions of profile in the child CPU classes.
Diffstat (limited to 'src/cpu/simple/TimingSimpleCPU.py')
-rw-r--r--src/cpu/simple/TimingSimpleCPU.py2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index f2b14a175..b7f044bfa 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -34,8 +34,6 @@ class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
_mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']