diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:24 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:24 -0800 |
| commit | f17f3d20be08d25f176138691a29897df54e5cc0 (patch) | |
| tree | b10a30a948462b94c5f1b9001fb7dc314d32cf32 /src/cpu/simple/TimingSimpleCPU.py | |
| parent | 7a39457d7ff5fd80484061a4ff7006921899b229 (diff) | |
| download | gem5-f17f3d20be08d25f176138691a29897df54e5cc0.tar.xz | |
X86: Implement a page table walker.
--HG--
extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
Diffstat (limited to 'src/cpu/simple/TimingSimpleCPU.py')
| -rw-r--r-- | src/cpu/simple/TimingSimpleCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 2fcde175c..7e777e813 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -38,4 +38,4 @@ class TimingSimpleCPU(BaseCPU): profile = Param.Latency('0ns', "trace the kernel stack") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] + _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port'] |