CPU: Get rid of translate... functions from various interface classes.

1 files changed, 2 insertions, 115 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index feb8a7fc5..cd07a9fe3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->translateDataReadReq(req);
+        Fault fault = thread->dtb->translate(req, tc, false);
 
         // Now do the access.
         if (fault == NoFault) {
@@ -370,61 +370,6 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
     }
 }
 
-Fault
-AtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr,
-        int size, unsigned flags)
-{
-    // use the CPU's statically allocated read request and packet objects
-    Request *req = &data_read_req;
-
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    //The block size of our peer.
-    int blockSize = dcachePort.peerBlockSize();
-    //The size of the data we're trying to read.
-    int dataSize = size;
-
-    bool firstTimeThrough = true;
-
-    //The address of the second part of this access if it needs to be split
-    //across a cache line boundary.
-    Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize);
-
-    if(secondAddr > vaddr)
-        dataSize = secondAddr - vaddr;
-
-    while(1) {
-        req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
-
-        // translate to physical address
-        Fault fault = thread->translateDataReadReq(req);
-
-        //If there's a fault, return it
-        if (fault != NoFault)
-            return fault;
-
-        if (firstTimeThrough) {
-            paddr = req->getPaddr();
-            firstTimeThrough = false;
-        }
-
-        //If we don't need to access a second cache line, stop now.
-        if (secondAddr <= vaddr)
-            return fault;
-
-        /*
-         * Set up for accessing the second cache line.
-         */
-
-        //Adjust the size to get the remaining bytes.
-        dataSize = vaddr + size - secondAddr;
-        //And access the right address.
-        vaddr = secondAddr;
-    }
-}
-
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
 template
@@ -507,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->translateDataWriteReq(req);
+        Fault fault = thread->dtb->translate(req, tc, true);
 
         // Now do the access.
         if (fault == NoFault) {
@@ -586,64 +531,6 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     }
 }
 
-Fault
-AtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    // use the CPU's statically allocated write request and packet objects
-    Request *req = &data_write_req;
-
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    //The block size of our peer.
-    int blockSize = dcachePort.peerBlockSize();
-
-    //The address of the second part of this access if it needs to be split
-    //across a cache line boundary.
-    Addr secondAddr = roundDown(vaddr + size - 1, blockSize);
-
-    //The size of the data we're trying to read.
-    int dataSize = size;
-
-    bool firstTimeThrough = true;
-
-    if(secondAddr > vaddr)
-        dataSize = secondAddr - vaddr;
-
-    dcache_latency = 0;
-
-    while(1) {
-        req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
-
-        // translate to physical address
-        Fault fault = thread->translateDataWriteReq(req);
-
-        //If there's a fault or we don't need to access a second cache line,
-        //stop now.
-        if (fault != NoFault)
-            return fault;
-
-        if (firstTimeThrough) {
-            paddr = req->getPaddr();
-            firstTimeThrough = false;
-        }
-
-        if (secondAddr <= vaddr)
-            return fault;
-
-        /*
-         * Set up for accessing the second cache line.
-         */
-
-        //Adjust the size to get the remaining bytes.
-        dataSize = vaddr + size - secondAddr;
-        //And access the right address.
-        vaddr = secondAddr;
-    }
-}
-
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS