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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 21:45:40 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 21:45:40 -0700 |
| commit | 7227ab5f223eb5f4d3ce80ea16bff5f87c3300b6 (patch) | |
| tree | 3f6c407eccafc56c85a6077fd05f4e98f7e6f034 /src/cpu/simple/atomic.cc | |
| parent | 8d1c7a83d7c052ba312a21ff6c6b8967b1e4b5f4 (diff) | |
| download | gem5-7227ab5f223eb5f4d3ce80ea16bff5f87c3300b6.tar.xz | |
Merge with head
--HG--
extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
Diffstat (limited to 'src/cpu/simple/atomic.cc')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 234803be5..06f52e30e 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -328,6 +328,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) dcache_latency += dcachePort.sendAtomic(&pkt); } dcache_access = true; + assert(!pkt.isError()); if (req->isLocked()) { @@ -611,6 +612,7 @@ AtomicSimpleCPU::tick() else icache_latency = icachePort.sendAtomic(&ifetch_pkt); + assert(!ifetch_pkt.isError()); // ifetch_req is initialized to read the instruction directly // into the CPU object's inst field. |