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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-05 12:39:21 -0500 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-05 12:39:21 -0500 |
commit | 8615b27174ae06db4665016c877b1e88031af203 (patch) | |
tree | 7b28888f71e7e41e84d4087b6ccb53670e04582b /src/cpu/simple/atomic.cc | |
parent | 76ee011a12ade238d5cbf4b570e1d34d7ba72687 (diff) | |
download | gem5-8615b27174ae06db4665016c877b1e88031af203.tar.xz |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r-- | src/cpu/simple/atomic.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 3cd6c1666..a8e97f14c 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -87,9 +87,9 @@ AtomicSimpleCPU::init() BaseSimpleCPU::init(); int cid = threadContexts[0]->contextId(); - ifetch_req.setThreadContext(cid, 0); - data_read_req.setThreadContext(cid, 0); - data_write_req.setThreadContext(cid, 0); + ifetch_req.setContext(cid); + data_read_req.setContext(cid); + data_write_req.setContext(cid); } AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) @@ -557,9 +557,9 @@ AtomicSimpleCPU::tick() if (numThreads > 1) { ContextID cid = threadContexts[curThread]->contextId(); - ifetch_req.setThreadContext(cid, curThread); - data_read_req.setThreadContext(cid, curThread); - data_write_req.setThreadContext(cid, curThread); + ifetch_req.setContext(cid); + data_read_req.setContext(cid); + data_write_req.setContext(cid); } SimpleExecContext& t_info = *threadInfo[curThread]; |