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author | Kevin Lim <ktlim@umich.edu> | 2006-06-29 19:45:53 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-06-29 19:45:53 -0400 |
commit | 77d0c0e28ac842e06e20a7861daf8a791680d797 (patch) | |
tree | 24a73d9f4da4f69cef702b7f8b06f03e61cff355 /src/cpu/simple/atomic.cc | |
parent | 2416ba606aed95098ce8e43f813fa57dd9f91974 (diff) | |
parent | 833d80db2d3119d85038b77360f8e25222b1e3f2 (diff) | |
download | gem5-77d0c0e28ac842e06e20a7861daf8a791680d797.tar.xz |
Merge ktlim@zamp:/z/ktlim2/clean/newmem-merge
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision : 9e21cdbb4fce8d9eb5f92780b720c42c44b6dd57
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r-- | src/cpu/simple/atomic.cc | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 7be74e97e..be6f421b3 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -407,15 +407,14 @@ AtomicSimpleCPU::tick() postExecute(); if (simulate_stalls) { - // This calculation assumes that the icache and dcache - // access latencies are always a multiple of the CPU's - // cycle time. If not, the next tick event may get - // scheduled at a non-integer multiple of the CPU - // cycle time. Tick icache_stall = icache_latency - cycles(1); Tick dcache_stall = dcache_access ? dcache_latency - cycles(1) : 0; - latency += icache_stall + dcache_stall; + Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); + if (cycles(stall_cycles) < (icache_stall + dcache_stall)) + latency += cycles(stall_cycles+1); + else + latency += cycles(stall_cycles); } } |