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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:16:15 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:16:15 -0800 |
| commit | 6ed47e94644f854baa33d1e9f367cc9eebd99abf (patch) | |
| tree | bc19d10504d3ef0bcaa56b6256cfc732897d1531 /src/cpu/simple/atomic.cc | |
| parent | 15940d06b5f6aabbe917a2a8c4cc4bb1cab991e2 (diff) | |
| download | gem5-6ed47e94644f854baa33d1e9f367cc9eebd99abf.tar.xz | |
CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.
Diffstat (limited to 'src/cpu/simple/atomic.cc')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 7a1cf71c4..2ada12b8d 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -607,8 +607,10 @@ AtomicSimpleCPU::tick() Fault fault = NoFault; bool fromRom = isRomMicroPC(thread->readMicroPC()); - if (!fromRom) - fault = setupFetchRequest(&ifetch_req); + if (!fromRom) { + setupFetchRequest(&ifetch_req); + fault = thread->itb->translateAtomic(&ifetch_req, tc); + } if (fault == NoFault) { Tick icache_latency = 0; |