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author | Gabe Black <gblack@eecs.umich.edu> | 2007-10-22 14:30:45 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-10-22 14:30:45 -0700 |
commit | 93da9eb7f6d9b2ca84de74afd3e0cb07188db9e6 (patch) | |
tree | c4584185c1f9ed37266e927ba112092dd881eb11 /src/cpu/simple/atomic.cc | |
parent | 43cb78004b73c3f98f3429cebb3f846a0f6ac8d3 (diff) | |
download | gem5-93da9eb7f6d9b2ca84de74afd3e0cb07188db9e6.tar.xz |
CPU: Add functions to the "ExecContext"s that translate a given address.
--HG--
extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r-- | src/cpu/simple/atomic.cc | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 9f574e8be..4e52f9b33 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -366,6 +366,61 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) } } +Fault +AtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr, + int size, unsigned flags) +{ + // use the CPU's statically allocated read request and packet objects + Request *req = &data_read_req; + + if (traceData) { + traceData->setAddr(vaddr); + } + + //The block size of our peer. + int blockSize = dcachePort.peerBlockSize(); + //The size of the data we're trying to read. + int dataSize = size; + + bool firstTimeThrough = true; + + //The address of the second part of this access if it needs to be split + //across a cache line boundary. + Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize); + + if(secondAddr > vaddr) + dataSize = secondAddr - vaddr; + + while(1) { + req->setVirt(0, vaddr, dataSize, flags, thread->readPC()); + + // translate to physical address + Fault fault = thread->translateDataReadReq(req); + + //If there's a fault, return it + if (fault != NoFault) + return fault; + + if (firstTimeThrough) { + paddr = req->getPaddr(); + firstTimeThrough = false; + } + + //If we don't need to access a second cache line, stop now. + if (secondAddr <= vaddr) + return fault; + + /* + * Set up for accessing the second cache line. + */ + + //Adjust the size to get the remaining bytes. + dataSize = vaddr + size - secondAddr; + //And access the right address. + vaddr = secondAddr; + } +} + #ifndef DOXYGEN_SHOULD_SKIP_THIS template @@ -524,6 +579,64 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } } +Fault +AtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags) +{ + // use the CPU's statically allocated write request and packet objects + Request *req = &data_write_req; + + if (traceData) { + traceData->setAddr(vaddr); + } + + //The block size of our peer. + int blockSize = dcachePort.peerBlockSize(); + + //The address of the second part of this access if it needs to be split + //across a cache line boundary. + Addr secondAddr = roundDown(vaddr + size - 1, blockSize); + + //The size of the data we're trying to read. + int dataSize = size; + + bool firstTimeThrough = true; + + if(secondAddr > vaddr) + dataSize = secondAddr - vaddr; + + dcache_latency = 0; + + while(1) { + req->setVirt(0, vaddr, flags, flags, thread->readPC()); + + // translate to physical address + Fault fault = thread->translateDataWriteReq(req); + + //If there's a fault or we don't need to access a second cache line, + //stop now. + if (fault != NoFault) + return fault; + + if (firstTimeThrough) { + paddr = req->getPaddr(); + firstTimeThrough = false; + } + + if (secondAddr <= vaddr) + return fault; + + /* + * Set up for accessing the second cache line. + */ + + //Adjust the size to get the remaining bytes. + dataSize = vaddr + size - secondAddr; + //And access the right address. + vaddr = secondAddr; + } +} + #ifndef DOXYGEN_SHOULD_SKIP_THIS |