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authorGabe Black <gblack@eecs.umich.edu>2007-06-19 18:17:34 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-06-19 18:17:34 +0000
commitea70e6d6daee29e7a4780d4b48f8140220ee2576 (patch)
tree3a494cf9de26a8319acfa6087186d03ad5bafb1b /src/cpu/simple/atomic.cc
parentd49649279312fe8d05c27a91f94992d8d584c35b (diff)
downloadgem5-ea70e6d6daee29e7a4780d4b48f8140220ee2576.tar.xz
Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.
--HG-- extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r--src/cpu/simple/atomic.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ea1c7d87f..03ff1282b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -521,15 +521,15 @@ AtomicSimpleCPU::tick()
dcache_access = false; // assume no dcache access
//Fetch more instruction memory if necessary
- if(predecoder.needMoreBytes())
- {
+ //if(predecoder.needMoreBytes())
+ //{
icache_access = true;
ifetch_pkt->reinitFromRequest();
icache_latency = icachePort.sendAtomic(ifetch_pkt);
// ifetch_req is initialized to read the instruction directly
// into the CPU object's inst field.
- }
+ //}
preExecute();