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author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 04:50:07 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 04:50:07 -0700 |
commit | 1a8a765a5c2f7aeca0569ca8b7e7f653aaa9d8d7 (patch) | |
tree | 2156f16fab4fb55b07425b1c27001e0819175d80 /src/cpu/simple/atomic.cc | |
parent | 742c3f045eb1821392a789a000ec89e802d6a4fd (diff) | |
download | gem5-1a8a765a5c2f7aeca0569ca8b7e7f653aaa9d8d7.tar.xz |
CPUs: Make the atomic CPU support locked memory accesses.
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r-- | src/cpu/simple/atomic.cc | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 045b0160f..eccdb2443 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -153,7 +153,7 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port) } AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) - : BaseSimpleCPU(p), tickEvent(this), width(p->width), + : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), simulate_data_stalls(p->simulate_data_stalls), simulate_inst_stalls(p->simulate_inst_stalls), icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), @@ -176,6 +176,7 @@ AtomicSimpleCPU::serialize(ostream &os) { SimObject::State so_state = SimObject::getState(); SERIALIZE_ENUM(so_state); + SERIALIZE_SCALAR(locked); BaseSimpleCPU::serialize(os); nameOut(os, csprintf("%s.tickEvent", name())); tickEvent.serialize(os); @@ -186,6 +187,7 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) { SimObject::State so_state; UNSERIALIZE_ENUM(so_state); + UNSERIALIZE_SCALAR(locked); BaseSimpleCPU::unserialize(cp, section); tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); } @@ -357,6 +359,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) if (traceData) { traceData->setData(data); } + if (req->isLocked() && fault == NoFault) { + assert(!locked); + locked = true; + } return fault; } @@ -518,6 +524,10 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) if (traceData) { traceData->setData(gtoh(data)); } + if (req->isLocked() && fault == NoFault) { + assert(locked); + locked = false; + } return fault; } @@ -599,7 +609,7 @@ AtomicSimpleCPU::tick() Tick latency = 0; - for (int i = 0; i < width; ++i) { + for (int i = 0; i < width || locked; ++i) { numCycles++; if (!curStaticInst || !curStaticInst->isDelayedCommit()) |