diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/cpu/simple/atomic.cc | |
parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r-- | src/cpu/simple/atomic.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 24e2f1eb8..4b243e862 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -269,7 +269,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, dcache_latency = 0; while (1) { - req->setVirt(0, addr, size, flags, thread->pcState().instAddr()); + req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); // translate to physical address Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); @@ -357,7 +357,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, dcache_latency = 0; while(1) { - req->setVirt(0, addr, size, flags, thread->pcState().instAddr()); + req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); // translate to physical address Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); |