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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-12 13:22:36 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-02-12 13:22:36 -0500 |
commit | b9005f35621c564fb70b60223352732eb9cde955 (patch) | |
tree | 0e1dc7cbbefbcf829a0c0cae92095c6255299915 /src/cpu/simple/atomic.cc | |
parent | ad17b3265178deacb2dce7a98033575c0e98f518 (diff) | |
parent | b5a4d95811db487d946200bf103e2af376db7690 (diff) | |
download | gem5-b9005f35621c564fb70b60223352732eb9cde955.tar.xz |
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
src/cpu/simple/atomic.cc:
merge steve's changes in.
--HG--
extra : convert_revision : a17eda37cd63c9380af6fe68b0aef4b1e1974231
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r-- | src/cpu/simple/atomic.cc | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 6a536fbcd..072867536 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -31,6 +31,7 @@ #include "arch/locked_mem.hh" #include "arch/mmaped_ipr.hh" #include "arch/utility.hh" +#include "base/bigint.hh" #include "cpu/exetrace.hh" #include "cpu/simple/atomic.hh" #include "mem/packet.hh" @@ -151,6 +152,8 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p) data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq, Packet::Broadcast); + data_swap_pkt = new Packet(data_write_req, MemCmd::SwapReq, + Packet::Broadcast); } @@ -318,6 +321,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) template Fault +AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); + +template +Fault AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); template @@ -363,10 +370,15 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) { // use the CPU's statically allocated write request and packet objects Request *req = data_write_req; - PacketPtr pkt = data_write_pkt; + PacketPtr pkt; req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); + if (req->isSwap()) + pkt = data_swap_pkt; + else + pkt = data_write_pkt; + if (traceData) { traceData->setAddr(addr); } @@ -381,6 +393,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) if (req->isLocked()) { do_access = TheISA::handleLockedWrite(thread, req); } + if (req->isCondSwap()) { + assert(res); + req->setExtraData(*res); + } + if (do_access) { pkt->reinitFromRequest(); @@ -401,7 +418,10 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) #endif } - if (res) { + if (req->isSwap()) { + assert(res); + *res = pkt->get<T>(); + } else if (res) { *res = req->getScResult(); } } |