Fixes for TimingSimpleCPU under full system. Now boots Alpha Linux!

src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
    Move traceData->finalize() into postExecute().
src/cpu/simple/timing.cc:
    Fixes for full system.  Now boots Alpha Linux!
    - Handle ifetch faults, suspend/resume.
    - Delete memory request & packet objects on response.
    - Don't try to do split memory accesses on prefetch references
    (ISA description doesn't support this).
src/cpu/simple/timing.hh:
    Minor reorganization of internal methods.

--HG--
extra : convert_revision : 59e3ee5e4cb53c424ebdbe2e504d97e88c08a978

1 files changed, 0 insertions, 4 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ec629304b..3cad6e43f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -425,10 +425,6 @@ AtomicSimpleCPU::tick()
             fault = curStaticInst->execute(this, traceData);
             postExecute();
 
-            if (traceData) {
-                traceData->finalize();
-            }
-
             if (simulate_stalls) {
                 // This calculation assumes that the icache and dcache
                 // access latencies are always a multiple of the CPU's