Merge zizzer:/bk/newmem

into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c358d5e3211756bbf905eef2a62b65a2e56a86f3

1 files changed, 11 insertions, 3 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 8cfe2ee83..67611e815 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -29,6 +29,7 @@
  */
 
 #include "arch/locked_mem.hh"
+#include "arch/mmaped_ipr.hh"
 #include "arch/utility.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/simple/atomic.hh"
@@ -289,7 +290,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
     if (fault == NoFault) {
         pkt->reinitFromRequest();
 
-        dcache_latency = dcachePort.sendAtomic(pkt);
+        if (req->isMmapedIpr())
+            dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
+        else
+            dcache_latency = dcachePort.sendAtomic(pkt);
         dcache_access = true;
 
         assert(pkt->result == Packet::Success);
@@ -376,11 +380,15 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         }
 
         if (do_access) {
-            data = htog(data);
             pkt->reinitFromRequest();
             pkt->dataStatic(&data);
 
-            dcache_latency = dcachePort.sendAtomic(pkt);
+            if (req->isMmapedIpr()) {
+                dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
+            } else {
+                data = htog(data);
+                dcache_latency = dcachePort.sendAtomic(pkt);
+            }
             dcache_access = true;
 
             assert(pkt->result == Packet::Success);