summaryrefslogtreecommitdiff
path: root/src/cpu/simple/atomic.cc
diff options
context:
space:
mode:
authorDam Sunwoo <dam.sunwoo@arm.com>2014-01-24 15:29:30 -0600
committerDam Sunwoo <dam.sunwoo@arm.com>2014-01-24 15:29:30 -0600
commit85e8779de78ed913bb6d2a794bee5252d719b0e5 (patch)
tree8ebd9519b4a6b0590c4d675061a0d1d4b43a1928 /src/cpu/simple/atomic.cc
parent739c6df94ea0030fea04065e6b8d8a1e232752a0 (diff)
downloadgem5-85e8779de78ed913bb6d2a794bee5252d719b0e5.tar.xz
mem: per-thread cache occupancy and per-block ages
This patch enables tracking of cache occupancy per thread along with ages (in buckets) per cache blocks. Cache occupancy stats are recalculated on each stat dump.
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r--src/cpu/simple/atomic.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 13c4b9bd3..617e845a5 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -301,6 +301,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
dcache_latency = 0;
+ req->taskId(taskId());
while (1) {
req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
@@ -387,6 +388,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
dcache_latency = 0;
+ req->taskId(taskId());
while(1) {
req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
@@ -492,6 +494,7 @@ AtomicSimpleCPU::tick()
bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
!curMacroStaticInst;
if (needToFetch) {
+ ifetch_req.taskId(taskId());
setupFetchRequest(&ifetch_req);
fault = thread->itb->translateAtomic(&ifetch_req, tc,
BaseTLB::Execute);