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authorAndreas Sandberg <andreas.sandberg@arm.com>2016-04-06 19:43:31 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2016-04-06 19:43:31 +0100
commitbe28d96510e0e722db83b26f1a12d3f5de979b32 (patch)
tree6a7e1807397f002f51fddb34568b89250fca45c8 /src/cpu/simple/atomic.cc
parent8615b27174ae06db4665016c877b1e88031af203 (diff)
downloadgem5-be28d96510e0e722db83b26f1a12d3f5de979b32.tar.xz
Revert power patch sets with unexpected interactions
The following patches had unexpected interactions with the current upstream code and have been reverted for now: e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r--src/cpu/simple/atomic.cc15
1 files changed, 6 insertions, 9 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index a8e97f14c..f3e14d401 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -87,9 +87,9 @@ AtomicSimpleCPU::init()
BaseSimpleCPU::init();
int cid = threadContexts[0]->contextId();
- ifetch_req.setContext(cid);
- data_read_req.setContext(cid);
- data_write_req.setContext(cid);
+ ifetch_req.setThreadContext(cid, 0);
+ data_read_req.setThreadContext(cid, 0);
+ data_write_req.setThreadContext(cid, 0);
}
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
@@ -247,8 +247,6 @@ AtomicSimpleCPU::activateContext(ThreadID thread_num)
== activeThreads.end()) {
activeThreads.push_back(thread_num);
}
-
- BaseCPU::activateContext(thread_num);
}
@@ -275,7 +273,6 @@ AtomicSimpleCPU::suspendContext(ThreadID thread_num)
}
}
- BaseCPU::suspendContext(thread_num);
}
@@ -557,9 +554,9 @@ AtomicSimpleCPU::tick()
if (numThreads > 1) {
ContextID cid = threadContexts[curThread]->contextId();
- ifetch_req.setContext(cid);
- data_read_req.setContext(cid);
- data_write_req.setContext(cid);
+ ifetch_req.setThreadContext(cid, curThread);
+ data_read_req.setThreadContext(cid, curThread);
+ data_write_req.setThreadContext(cid, curThread);
}
SimpleExecContext& t_info = *threadInfo[curThread];