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authorSteve Reinhardt <stever@eecs.umich.edu>2006-10-08 10:43:31 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2006-10-08 10:43:31 -0700
commitbe36c808f77cfcb001aacb8cb32f45fb5909e00e (patch)
tree63f2ec345f3ec01afa85de33dc2c79b7255f7646 /src/cpu/simple/atomic.cc
parentc2f954ac692e664ba105f94c64c8c408cf1b4380 (diff)
downloadgem5-be36c808f77cfcb001aacb8cb32f45fb5909e00e.tar.xz
Rename some vars for clarity.
--HG-- extra : convert_revision : 765283ae54d2d6b5885ea44c6c1813d4bcf18488
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r--src/cpu/simple/atomic.cc41
1 files changed, 24 insertions, 17 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 88698bfee..1b67af81b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -253,29 +253,32 @@ template <class T>
Fault
AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
- data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
+ // use the CPU's statically allocated read request and packet objects
+ Request *req = data_read_req;
+ Packet *pkt = data_read_pkt;
+
+ req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
if (traceData) {
traceData->setAddr(addr);
}
// translate to physical address
- Fault fault = thread->translateDataReadReq(data_read_req);
+ Fault fault = thread->translateDataReadReq(req);
// Now do the access.
if (fault == NoFault) {
- data_read_pkt->reinitFromRequest();
+ pkt->reinitFromRequest();
- dcache_latency = dcachePort.sendAtomic(data_read_pkt);
+ dcache_latency = dcachePort.sendAtomic(pkt);
dcache_access = true;
- assert(data_read_pkt->result == Packet::Success);
- data = data_read_pkt->get<T>();
-
+ assert(pkt->result == Packet::Success);
+ data = pkt->get<T>();
}
// This will need a new way to tell if it has a dcache attached.
- if (data_read_req->getFlags() & UNCACHEABLE)
+ if (req->getFlags() & UNCACHEABLE)
recordEvent("Uncached Read");
return fault;
@@ -328,33 +331,37 @@ template <class T>
Fault
AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
+ // use the CPU's statically allocated write request and packet objects
+ Request *req = data_write_req;
+ Packet *pkt = data_write_pkt;
+
+ req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
if (traceData) {
traceData->setAddr(addr);
}
// translate to physical address
- Fault fault = thread->translateDataWriteReq(data_write_req);
+ Fault fault = thread->translateDataWriteReq(req);
// Now do the access.
if (fault == NoFault) {
data = htog(data);
- data_write_pkt->reinitFromRequest();
- data_write_pkt->dataStatic(&data);
+ pkt->reinitFromRequest();
+ pkt->dataStatic(&data);
- dcache_latency = dcachePort.sendAtomic(data_write_pkt);
+ dcache_latency = dcachePort.sendAtomic(pkt);
dcache_access = true;
- assert(data_write_pkt->result == Packet::Success);
+ assert(pkt->result == Packet::Success);
- if (res && data_write_req->getFlags() & LOCKED) {
- *res = data_write_req->getScResult();
+ if (res && req->getFlags() & LOCKED) {
+ *res = req->getScResult();
}
}
// This will need a new way to tell if it's hooked up to a cache or not.
- if (data_write_req->getFlags() & UNCACHEABLE)
+ if (req->getFlags() & UNCACHEABLE)
recordEvent("Uncached Write");
// If the write needs to have a fault on the access, consider calling