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authorMitch Hayenga <mitch.hayenga@arm.com>2016-04-07 09:30:20 -0500
committerMitch Hayenga <mitch.hayenga@arm.com>2016-04-07 09:30:20 -0500
commitc75ff71139d6358678835cca63e35d1135eaf466 (patch)
tree0811177db4dca4a237b8e5d7dd65f8ec155cb14e /src/cpu/simple/atomic.cc
parentd99deff8ea296fd28b48da08aba577a1e7dfc01b (diff)
downloadgem5-c75ff71139d6358678835cca63e35d1135eaf466.tar.xz
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit.
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r--src/cpu/simple/atomic.cc12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index f3e14d401..3996b33ca 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -87,9 +87,9 @@ AtomicSimpleCPU::init()
BaseSimpleCPU::init();
int cid = threadContexts[0]->contextId();
- ifetch_req.setThreadContext(cid, 0);
- data_read_req.setThreadContext(cid, 0);
- data_write_req.setThreadContext(cid, 0);
+ ifetch_req.setContext(cid);
+ data_read_req.setContext(cid);
+ data_write_req.setContext(cid);
}
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
@@ -554,9 +554,9 @@ AtomicSimpleCPU::tick()
if (numThreads > 1) {
ContextID cid = threadContexts[curThread]->contextId();
- ifetch_req.setThreadContext(cid, curThread);
- data_read_req.setThreadContext(cid, curThread);
- data_write_req.setThreadContext(cid, curThread);
+ ifetch_req.setContext(cid);
+ data_read_req.setContext(cid);
+ data_write_req.setContext(cid);
}
SimpleExecContext& t_info = *threadInfo[curThread];