diff options
author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-30 22:30:42 -0400 |
---|---|---|
committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-30 22:30:42 -0400 |
commit | 91e3aa629550fcdaa03173f94674a74ac906ae4c (patch) | |
tree | 74be65e6ad56201467cae3f278ebf83eff3b8785 /src/cpu/simple/atomic.cc | |
parent | 0e5db091e91d576bd5b05d22103115496084bd19 (diff) | |
download | gem5-91e3aa629550fcdaa03173f94674a74ac906ae4c.tar.xz |
Minor further cleanup & commenting of Packet class.
src/cpu/simple/atomic.cc:
Make common ifetch setup based on Request rather than Packet.
Packet::reset() no longer a separate function.
sendAtomic() returns latency, not absolute tick.
src/cpu/simple/atomic.hh:
sendAtomic returns latency, not absolute tick.
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
Make common ifetch setup based on Request rather than Packet.
src/dev/alpha_console.cc:
src/dev/ide_ctrl.cc:
src/dev/io_device.cc:
src/dev/isa_fake.cc:
src/dev/ns_gige.cc:
src/dev/pciconfigall.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/dev/tsunami_io.cc:
src/dev/tsunami_pchip.cc:
src/dev/uart8250.cc:
src/mem/physical.cc:
Get rid of redundant Packet time field.
src/mem/packet.cc:
Eliminate reset() method.
src/mem/packet.hh:
Fold reset() function into reinitFromRequest()... it was
only ever called together with that function.
Get rid of redundant time field.
Cleanup/add comments.
src/mem/port.hh:
Document in comment that sendAtomic returns latency, not absolute tick.
--HG--
extra : convert_revision : 0252f1a294043ca3ed58f437232ad24fc0733e0c
Diffstat (limited to 'src/cpu/simple/atomic.cc')
-rw-r--r-- | src/cpu/simple/atomic.cc | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index a0d26a8ab..c2e6f6185 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -250,10 +250,9 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) // Now do the access. if (fault == NoFault) { - data_read_pkt->reset(); data_read_pkt->reinitFromRequest(); - dcache_complete = dcachePort.sendAtomic(data_read_pkt); + dcache_latency = dcachePort.sendAtomic(data_read_pkt); dcache_access = true; assert(data_read_pkt->result == Packet::Success); @@ -329,12 +328,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) // Now do the access. if (fault == NoFault) { - data_write_pkt->reset(); data = htog(data); - data_write_pkt->dataStatic(&data); data_write_pkt->reinitFromRequest(); + data_write_pkt->dataStatic(&data); - dcache_complete = dcachePort.sendAtomic(data_write_pkt); + dcache_latency = dcachePort.sendAtomic(data_write_pkt); dcache_access = true; assert(data_write_pkt->result == Packet::Success); @@ -411,11 +409,12 @@ AtomicSimpleCPU::tick() checkForInterrupts(); ifetch_req->resetMin(); - ifetch_pkt->reset(); - Fault fault = setupFetchPacket(ifetch_pkt); + Fault fault = setupFetchRequest(ifetch_req); if (fault == NoFault) { - Tick icache_complete = icachePort.sendAtomic(ifetch_pkt); + ifetch_pkt->reinitFromRequest(); + + Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); // ifetch_req is initialized to read the instruction directly // into the CPU object's inst field. @@ -430,9 +429,9 @@ AtomicSimpleCPU::tick() // cycle time. If not, the next tick event may get // scheduled at a non-integer multiple of the CPU // cycle time. - Tick icache_stall = icache_complete - curTick - cycles(1); + Tick icache_stall = icache_latency - cycles(1); Tick dcache_stall = - dcache_access ? dcache_complete - curTick - cycles(1) : 0; + dcache_access ? dcache_latency - cycles(1) : 0; latency += icache_stall + dcache_stall; } |