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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 21:44:15 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 21:44:15 -0700 |
| commit | bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350 (patch) | |
| tree | 5492dc138704c1c3da4592a42f6a45be904e0188 /src/cpu/simple/atomic.cc | |
| parent | 089b3840865f816493a33f2ccf987307d0a79f87 (diff) | |
| download | gem5-bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350.tar.xz | |
Mem: Change isLlsc to isLLSC.
Diffstat (limited to 'src/cpu/simple/atomic.cc')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index eccdb2443..045b80c80 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -324,7 +324,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) // Now do the access. if (fault == NoFault) { Packet pkt = Packet(req, - req->isLlsc() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, + req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, Packet::Broadcast); pkt.dataStatic(dataPtr); @@ -340,7 +340,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) assert(!pkt.isError()); - if (req->isLlsc()) { + if (req->isLLSC()) { TheISA::handleLockedRead(thread, req); } } @@ -468,7 +468,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) MemCmd cmd = MemCmd::WriteReq; // default bool do_access = true; // flag to suppress cache access - if (req->isLlsc()) { + if (req->isLLSC()) { cmd = MemCmd::StoreCondReq; do_access = TheISA::handleLockedWrite(thread, req); } else if (req->isSwap()) { |