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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-27 15:48:22 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-12-11 15:07:52 +0000 |
| commit | c3bd8eb1214cbebbc92c7958b80aa06913bce3ba (patch) | |
| tree | 6df53d30662ba49d93a1b90e3bfd1826bdb6726e /src/cpu/simple/atomic.cc | |
| parent | f73caae20fed7b4500a724ac85c20b637ee353a1 (diff) | |
| download | gem5-c3bd8eb1214cbebbc92c7958b80aa06913bce3ba.tar.xz | |
cpu: Fix coding style (byteEnable->byte_enable)
Change-Id: I2206559c6c2a6e6a0452e9c7d9964792afa9f358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23282
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/simple/atomic.cc')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 9052cee2e..3e3ba41b3 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -371,7 +371,7 @@ AtomicSimpleCPU::genMemFragmentRequest(const RequestPtr& req, Addr frag_addr, Fault AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, Request::Flags flags, - const std::vector<bool>& byteEnable) + const std::vector<bool>& byte_enable) { SimpleExecContext& t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; @@ -394,7 +394,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, while (1) { predicate = genMemFragmentRequest(req, frag_addr, size, flags, - byteEnable, frag_size, size_left); + byte_enable, frag_size, size_left); // translate to physical address if (predicate) { @@ -453,7 +453,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, Fault AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector<bool>& byteEnable) + const std::vector<bool>& byte_enable) { SimpleExecContext& t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; @@ -485,7 +485,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, while (1) { predicate = genMemFragmentRequest(req, frag_addr, size, flags, - byteEnable, frag_size, size_left); + byte_enable, frag_size, size_left); // translate to physical address if (predicate) @@ -541,7 +541,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, if (fault != NoFault || size_left == 0) { if (req->isLockedRMW() && fault == NoFault) { - assert(byteEnable.empty()); + assert(byte_enable.empty()); locked = false; } |