Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory

configs/test/test.py:
    Update to use new cpu getPort functionality
src/cpu/base.cc:
    Make cpu's a memObject to expose getPort interface
src/cpu/base.hh:
    Make cpu's a memObject to export getPort interface
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Now use the connector via getPort interface
src/mem/cache/base_cache.cc:
    Make sure the cache recognizes all port names

--HG--
extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61

1 files changed, 2 insertions, 0 deletions

diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 951a8da06..179b4a721 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -122,6 +122,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
   public:
 
+    virtual Port *getPort(const std::string &if_name, int idx = -1);
+
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);