cpu: generate SimPoint basic block vector profiles

This patch is based on http://reviews.m5sim.org/r/1474/ originally written by
Mitch Hayenga. Basic block vectors are generated (simpoint.bb.gz in simout
folder) based on start and end addresses of basic blocks.

Some comments to the original patch are addressed and hooks are added to create
and resume from checkpoints based on instruction counts dictated by external
SimPoint analysis tools.

SimPoint creation/resuming options will be implemented as a separate patch.

1 files changed, 66 insertions, 0 deletions

diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 9bb653bcc..5a9275a77 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -43,9 +43,31 @@
 #ifndef __CPU_SIMPLE_ATOMIC_HH__
 #define __CPU_SIMPLE_ATOMIC_HH__
 
+#include "base/hashmap.hh"
 #include "cpu/simple/base.hh"
 #include "params/AtomicSimpleCPU.hh"
 
+/**
+ *  Start and end address of basic block for SimPoint profiling.
+ *  This structure is used to look up the hash table of BBVs.
+ *  - first: PC of first inst in basic block
+ *  - second: PC of last inst in basic block
+ */
+typedef std::pair<Addr, Addr> BasicBlockRange;
+
+/** Overload hash function for BasicBlockRange type */
+__hash_namespace_begin
+template <>
+class hash<BasicBlockRange>
+{
+  public:
+    size_t operator()(const BasicBlockRange &bb) const {
+        return hash<Addr>()(bb.first + bb.second);
+    }
+};
+__hash_namespace_end
+
+
 class AtomicSimpleCPU : public BaseSimpleCPU
 {
   public:
@@ -161,6 +183,50 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     bool dcache_access;
     Tick dcache_latency;
 
+    /**
+     * Profile basic blocks for SimPoints.
+     * Called at every macro inst to increment basic block inst counts and
+     * to profile block if end of block.
+     */
+    void profileSimPoint();
+
+    /** Data structures for SimPoints BBV generation
+     *  @{
+     */
+
+    /** Whether SimPoint BBV profiling is enabled */
+    const bool simpoint;
+    /** SimPoint profiling interval size in instructions */
+    const uint64_t intervalSize;
+
+    /** Inst count in current basic block */
+    uint64_t intervalCount;
+    /** Excess inst count from previous interval*/
+    uint64_t intervalDrift;
+    /** Pointer to SimPoint BBV output stream */
+    std::ostream *simpointStream;
+
+    /** Basic Block information */
+    struct BBInfo {
+        /** Unique ID */
+        uint64_t id;
+        /** Num of static insts in BB */
+        uint64_t insts;
+        /** Accumulated dynamic inst count executed by BB */
+        uint64_t count;
+    };
+
+    /** Hash table containing all previously seen basic blocks */
+    m5::hash_map<BasicBlockRange, BBInfo> bbMap;
+    /** Currently executing basic block */
+    BasicBlockRange currentBBV;
+    /** inst count in current basic block */
+    uint64_t currentBBVInstCount;
+
+    /** @}
+     *  End of data structures for SimPoints BBV generation
+     */
+
   protected:
 
     /** Return a reference to the data port. */