diff options
author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-03-15 15:45:12 +0000 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-09-12 09:25:26 +0000 |
commit | 719eb033fe435133abf15501c249eec10d1c861f (patch) | |
tree | 2f6bb0f128c889b3503a9f6b8ce3b7fb69cbd3a5 /src/cpu/simple/atomic.hh | |
parent | 50cd8a53c640dbcc0cd775cb96c956572c880979 (diff) | |
download | gem5-719eb033fe435133abf15501c249eec10d1c861f.tar.xz |
cpu: Replace the fastmem with a new CPU model
The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.
The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.
This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.
Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/simple/atomic.hh')
-rw-r--r-- | src/cpu/simple/atomic.hh | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index addbe234e..a5151aa18 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013,2015 ARM Limited + * Copyright (c) 2012-2013, 2015, 2018 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -58,7 +58,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU void init() override; - private: + protected: EventFunctionWrapper tickEvent; @@ -103,6 +103,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU */ bool tryCompleteDrain(); + virtual Tick sendPacket(MasterPort &port, const PacketPtr &pkt); + /** * An AtomicCPUPort overrides the default behaviour of the * recvAtomicSnoop and ignores the packet instead of panicking. It @@ -137,7 +139,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU { public: - AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) : AtomicCPUPort(_name, _cpu), cpu(_cpu) { @@ -158,7 +159,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU AtomicCPUPort icachePort; AtomicCPUDPort dcachePort; - bool fastmem; + RequestPtr ifetch_req; RequestPtr data_read_req; RequestPtr data_write_req; |