CPU: Moving towards a more general port across CPU models

This patch performs minimal changes to move the instruction and data
ports from specialised subclasses to the base CPU (to the largest
degree possible). Ultimately it servers to make the CPU(s) have a
well-defined interface to the memory sub-system.

1 files changed, 15 insertions, 22 deletions

diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index c3d78a381..77a9d6b0d 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -64,38 +64,31 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     // main simulation loop (one cycle)
     void tick();
 
-    class CpuPort : public Port
+    /**
+     * An AtomicCPUPort overrides the default behaviour of the
+     * recvAtomic and ignores the packet instead of panicking.
+     */
+    class AtomicCPUPort : public CpuPort
     {
+
       public:
 
-        CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
-            : Port(_name, _cpu), cpu(_cpu)
+        AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
+            : CpuPort(_name, _cpu)
         { }
 
-        bool snoopRangeSent;
-
       protected:
 
-        AtomicSimpleCPU *cpu;
-
-        virtual bool recvTiming(PacketPtr pkt);
-
-        virtual Tick recvAtomic(PacketPtr pkt);
-
-        virtual void recvFunctional(PacketPtr pkt);
-
-        virtual void recvStatusChange(Status status);
-
-        virtual void recvRetry();
-
-        virtual void getDeviceAddressRanges(AddrRangeList &resp,
-            bool &snoop)
-        { resp.clear(); snoop = true; }
+        virtual Tick recvAtomic(PacketPtr pkt)
+        {
+            // Snooping a coherence request, just return
+            return 0;
+        }
 
     };
-    CpuPort icachePort;
 
-    CpuPort dcachePort;
+    AtomicCPUPort icachePort;
+    AtomicCPUPort dcachePort;
 
     CpuPort physmemPort;
     bool hasPhysMemPort;