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authorRon Dreslinski <rdreslin@umich.edu>2006-07-07 15:15:11 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-07-07 15:15:11 -0400
commitea11c7bdbefc8eb640f875cdf91a6d6bed398ec4 (patch)
tree3af6e347d31fffe724122db63ebff97aaf819c3e /src/cpu/simple/atomic.hh
parent1ccfdb442ff34f9f2b38ee7716b7baee99a397c2 (diff)
downloadgem5-ea11c7bdbefc8eb640f875cdf91a6d6bed398ec4.tar.xz
Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory
configs/test/test.py: Update to use new cpu getPort functionality src/cpu/base.cc: Make cpu's a memObject to expose getPort interface src/cpu/base.hh: Make cpu's a memObject to export getPort interface src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Now use the connector via getPort interface src/mem/cache/base_cache.cc: Make sure the cache recognizes all port names --HG-- extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
Diffstat (limited to 'src/cpu/simple/atomic.hh')
-rw-r--r--src/cpu/simple/atomic.hh2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 951a8da06..179b4a721 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -122,6 +122,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
+ virtual Port *getPort(const std::string &if_name, int idx = -1);
+
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);