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| author | Vincentius Robby <acolyte@umich.edu> | 2007-08-08 18:43:12 -0400 |
|---|---|---|
| committer | Vincentius Robby <acolyte@umich.edu> | 2007-08-08 18:43:12 -0400 |
| commit | ec4000e0e284834df0eb1db792074a1b11f21cc8 (patch) | |
| tree | 9b42b9697c8fe3cf00c3ab8257002146d8d37a9c /src/cpu/simple/atomic.hh | |
| parent | 1caed1465470269c36897904edddf8d4dc9765b1 (diff) | |
| download | gem5-ec4000e0e284834df0eb1db792074a1b11f21cc8.tar.xz | |
Added fastmem option.
Lets CPU accesses to physical memory bypass Bus.
--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
Diffstat (limited to 'src/cpu/simple/atomic.hh')
| -rw-r--r-- | src/cpu/simple/atomic.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 28e883b24..96429e5b1 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -121,6 +121,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU }; DcachePort dcachePort; + CpuPort physmemPort; + bool hasPhysMemPort; Request ifetch_req; Request data_read_req; Request data_write_req; @@ -128,6 +130,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU bool dcache_access; Tick dcache_latency; + Range<Addr> physMemAddr; + public: virtual Port *getPort(const std::string &if_name, int idx = -1); |