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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-04 09:40:19 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
commit | f54020eb8155371725ab75b0fc5c419287eca084 (patch) | |
tree | 65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/cpu/simple/atomic.hh | |
parent | 2113b21996d086dab32b9fd388efe3df241bfbd2 (diff) | |
download | gem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/simple/atomic.hh')
-rw-r--r-- | src/cpu/simple/atomic.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index c9dd954bb..addbe234e 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -159,9 +159,9 @@ class AtomicSimpleCPU : public BaseSimpleCPU AtomicCPUDPort dcachePort; bool fastmem; - Request ifetch_req; - Request data_read_req; - Request data_write_req; + RequestPtr ifetch_req; + RequestPtr data_read_req; + RequestPtr data_write_req; bool dcache_access; Tick dcache_latency; |