summaryrefslogtreecommitdiff
path: root/src/cpu/simple/base.cc
diff options
context:
space:
mode:
authorNathan Binkert <binkertn@umich.edu>2006-06-11 22:01:34 -0400
committerNathan Binkert <binkertn@umich.edu>2006-06-11 22:01:34 -0400
commit3c95f5958fd1a90cf83d85e1b24fb700c07bae91 (patch)
treeff0fba54297f66dd8e5ef7cbb46d09d8698ee08b /src/cpu/simple/base.cc
parent4ab8e881edecd47ae3f2ba5fda345f7ff9788870 (diff)
parent7af93dbdf6c86a915b99da1688f51dc12e7aafff (diff)
downloadgem5-3c95f5958fd1a90cf83d85e1b24fb700c07bae91.tar.xz
Merge iceaxe.:/Volumes/work/research/m5/head
into iceaxe.:/Volumes/work/research/m5/merge src/cpu/simple/base.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/python/m5/objects/System.py: src/sim/system.cc: src/sim/system.hh: hand merge --HG-- rename : build/SConstruct => SConstruct rename : SConscript => src/SConscript rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : base/statistics.cc => src/base/statistics.cc rename : base/statistics.hh => src/base/statistics.hh rename : base/stats/mysql.cc => src/base/stats/mysql.cc rename : base/stats/mysql.hh => src/base/stats/mysql.hh rename : base/stats/statdb.cc => src/base/stats/statdb.cc rename : base/stats/statdb.hh => src/base/stats/statdb.hh rename : base/stats/text.cc => src/base/stats/text.cc rename : base/stats/text.hh => src/base/stats/text.hh rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh rename : kern/system_events.cc => src/kern/system_events.cc rename : kern/system_events.hh => src/kern/system_events.hh rename : python/m5/objects/System.py => src/python/m5/objects/System.py rename : sim/system.cc => src/sim/system.cc rename : sim/system.hh => src/sim/system.hh rename : test/stattest.cc => src/unittest/stattest.cc extra : convert_revision : 4bb576a2bf5e32784efc48030bd776c6c7c29a7c
Diffstat (limited to 'src/cpu/simple/base.cc')
-rw-r--r--src/cpu/simple/base.cc5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index c1ecf3967..d94b0e079 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -409,11 +409,6 @@ void
BaseSimpleCPU::postExecute()
{
#if FULL_SYSTEM
- if (system->kernelBinning->fnbin) {
- assert(thread->getKernelStats());
- system->kernelBinning->execute(tc, inst);
- }
-
if (thread->profile) {
bool usermode =
(thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;