Reorganization/renaming of CPUExecContext. Now it is called SimpleThread in order to clear up the confusion due to the many ExecContexts. It also derives from a common ThreadState object, which holds various state common to threads across CPU models.

Following with the previous check-in, ExecContext now refers only to the interface provided to the ISA in order to access CPU state.  ThreadContext refers to the interface provided to all objects outside the CPU in order to access thread state.  SimpleThread provides all thread state and the interface to access it, and is suitable for simple execution models such as the SimpleCPU.

src/SConscript:
    Include thread state file.
src/arch/alpha/ev5.cc:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/thread_context.hh:
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/cpu.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    Rename CPUExecContext to SimpleThread.
src/cpu/base_dyn_inst.hh:
    Make thread member variables protected..
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/cpu.hh:
    Make various members of ThreadState protected.
src/cpu/o3/alpha_cpu_impl.hh:
    Push generation of TranslatingPort into the CPU itself.
    Make various members of ThreadState protected.
src/cpu/o3/thread_state.hh:
    Pull a lot of common code into the base ThreadState class.
src/cpu/ozone/thread_state.hh:
    Rename CPUExecContext to SimpleThread, move a lot of common code into base ThreadState class.
src/cpu/thread_state.hh:
    Push a lot of common code into base ThreadState class.  This goes along with renaming CPUExecContext to SimpleThread, and making it derive from ThreadState.
src/cpu/simple_thread.cc:
    Rename CPUExecContext to SimpleThread, make it derive from ThreadState.  This helps push a lot of common code/state into a single class that can be used by all CPUs.
src/cpu/simple_thread.hh:
    Rename CPUExecContext to SimpleThread, make it derive from ThreadState.
src/kern/system_events.cc:
    Rename cpu_exec_context to thread_context.
src/sim/process.hh:
    Remove unused forward declaration.

--HG--
rename : src/cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : src/cpu/cpu_exec_context.hh => src/cpu/simple_thread.hh
extra : convert_revision : 2ed617aa80b64016cb9270f75352607cca032733

1 files changed, 58 insertions, 58 deletions

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index d36aa93a2..c1ecf3967 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -38,18 +38,18 @@
 #include "base/stats/events.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
-#include "cpu/cpu_exec_context.hh"
-#include "cpu/thread_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/profile.hh"
 #include "cpu/sampler/sampler.hh"
 #include "cpu/simple/base.hh"
+#include "cpu/simple_thread.hh"
 #include "cpu/smt.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
 #include "kern/kernel_stats.hh"
 #include "mem/packet_impl.hh"
-#include "sim/byteswap.hh"
 #include "sim/builder.hh"
+#include "sim/byteswap.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"
 #include "sim/sim_events.hh"
@@ -70,18 +70,18 @@ using namespace std;
 using namespace TheISA;
 
 BaseSimpleCPU::BaseSimpleCPU(Params *p)
-    : BaseCPU(p), mem(p->mem), cpuXC(NULL)
+    : BaseCPU(p), mem(p->mem), thread(NULL)
 {
 #if FULL_SYSTEM
-    cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb);
+    thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
 #else
-    cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process,
+    thread = new SimpleThread(this, /* thread_num */ 0, p->process,
             /* asid */ 0, mem);
 #endif // !FULL_SYSTEM
 
-    cpuXC->setStatus(ThreadContext::Suspended);
+    thread->setStatus(ThreadContext::Suspended);
 
-    tc = cpuXC->getTC();
+    tc = thread->getTC();
 
     numInst = 0;
     startNumInst = 0;
@@ -180,7 +180,7 @@ BaseSimpleCPU::serialize(ostream &os)
     BaseCPU::serialize(os);
     SERIALIZE_SCALAR(inst);
     nameOut(os, csprintf("%s.xc", name()));
-    cpuXC->serialize(os);
+    thread->serialize(os);
 }
 
 void
@@ -188,7 +188,7 @@ BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 {
     BaseCPU::unserialize(cp, section);
     UNSERIALIZE_SCALAR(inst);
-    cpuXC->unserialize(cp, csprintf("%s.xc", section));
+    thread->unserialize(cp, csprintf("%s.xc", section));
 }
 
 void
@@ -217,16 +217,16 @@ BaseSimpleCPU::copySrcTranslate(Addr src)
     memReq->reset(src & ~(blk_size - 1), blk_size);
 
     // translate to physical address
-    Fault fault = cpuXC->translateDataReadReq(req);
+    Fault fault = thread->translateDataReadReq(req);
 
     if (fault == NoFault) {
-        cpuXC->copySrcAddr = src;
-        cpuXC->copySrcPhysAddr = memReq->paddr + offset;
+        thread->copySrcAddr = src;
+        thread->copySrcPhysAddr = memReq->paddr + offset;
     } else {
         assert(!fault->isAlignmentFault());
 
-        cpuXC->copySrcAddr = 0;
-        cpuXC->copySrcPhysAddr = 0;
+        thread->copySrcAddr = 0;
+        thread->copySrcPhysAddr = 0;
     }
     return fault;
 #else
@@ -243,7 +243,7 @@ BaseSimpleCPU::copy(Addr dest)
     // Only support block sizes of 64 atm.
     assert(blk_size == 64);
     uint8_t data[blk_size];
-    //assert(cpuXC->copySrcAddr);
+    //assert(thread->copySrcAddr);
     int offset = dest & (blk_size - 1);
 
     // Make sure block doesn't span page
@@ -256,19 +256,19 @@ BaseSimpleCPU::copy(Addr dest)
 
     memReq->reset(dest & ~(blk_size -1), blk_size);
     // translate to physical address
-    Fault fault = cpuXC->translateDataWriteReq(req);
+    Fault fault = thread->translateDataWriteReq(req);
 
     if (fault == NoFault) {
         Addr dest_addr = memReq->paddr + offset;
         // Need to read straight from memory since we have more than 8 bytes.
-        memReq->paddr = cpuXC->copySrcPhysAddr;
-        cpuXC->mem->read(memReq, data);
+        memReq->paddr = thread->copySrcPhysAddr;
+        thread->mem->read(memReq, data);
         memReq->paddr = dest_addr;
-        cpuXC->mem->write(memReq, data);
+        thread->mem->write(memReq, data);
         if (dcacheInterface) {
             memReq->cmd = Copy;
             memReq->completionEvent = NULL;
-            memReq->paddr = cpuXC->copySrcPhysAddr;
+            memReq->paddr = thread->copySrcPhysAddr;
             memReq->dest = dest_addr;
             memReq->size = 64;
             memReq->time = curTick;
@@ -300,9 +300,9 @@ BaseSimpleCPU::post_interrupt(int int_num, int index)
 {
     BaseCPU::post_interrupt(int_num, index);
 
-    if (cpuXC->status() == ThreadContext::Suspended) {
+    if (thread->status() == ThreadContext::Suspended) {
                 DPRINTF(IPI,"Suspended Processor awoke\n");
-        cpuXC->activate();
+        thread->activate();
     }
 }
 #endif // FULL_SYSTEM
@@ -311,15 +311,15 @@ void
 BaseSimpleCPU::checkForInterrupts()
 {
 #if FULL_SYSTEM
-    if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode()) {
+    if (checkInterrupts && check_interrupts() && !thread->inPalMode()) {
         int ipl = 0;
         int summary = 0;
         checkInterrupts = false;
 
-        if (cpuXC->readMiscReg(IPR_SIRR)) {
+        if (thread->readMiscReg(IPR_SIRR)) {
             for (int i = INTLEVEL_SOFTWARE_MIN;
                  i < INTLEVEL_SOFTWARE_MAX; i++) {
-                if (cpuXC->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+                if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
                     // See table 4-19 of 21164 hardware reference
                     ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                     summary |= (ULL(1) << i);
@@ -327,7 +327,7 @@ BaseSimpleCPU::checkForInterrupts()
             }
         }
 
-        uint64_t interrupts = cpuXC->cpu->intr_status();
+        uint64_t interrupts = thread->cpu->intr_status();
         for (int i = INTLEVEL_EXTERNAL_MIN;
             i < INTLEVEL_EXTERNAL_MAX; i++) {
             if (interrupts & (ULL(1) << i)) {
@@ -337,17 +337,17 @@ BaseSimpleCPU::checkForInterrupts()
             }
         }
 
-        if (cpuXC->readMiscReg(IPR_ASTRR))
+        if (thread->readMiscReg(IPR_ASTRR))
             panic("asynchronous traps not implemented\n");
 
-        if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) {
-            cpuXC->setMiscReg(IPR_ISR, summary);
-            cpuXC->setMiscReg(IPR_INTID, ipl);
+        if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
+            thread->setMiscReg(IPR_ISR, summary);
+            thread->setMiscReg(IPR_INTID, ipl);
 
             Fault(new InterruptFault)->invoke(tc);
 
             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                    cpuXC->readMiscReg(IPR_IPLR), ipl, summary);
+                    thread->readMiscReg(IPR_IPLR), ipl, summary);
         }
     }
 #endif
@@ -358,14 +358,14 @@ Fault
 BaseSimpleCPU::setupFetchRequest(Request *req)
 {
     // set up memory request for instruction fetch
-    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
-            cpuXC->readNextPC(),cpuXC->readNextNPC());
+    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
+            thread->readNextPC(),thread->readNextNPC());
 
-    req->setVirt(0, cpuXC->readPC() & ~3, sizeof(MachInst),
-                 (FULL_SYSTEM && (cpuXC->readPC() & 1)) ? PHYSICAL : 0,
-                 cpuXC->readPC());
+    req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
+                 (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0,
+                 thread->readPC());
 
-    Fault fault = cpuXC->translateInstReq(req);
+    Fault fault = thread->translateInstReq(req);
 
     return fault;
 }
@@ -375,33 +375,33 @@ void
 BaseSimpleCPU::preExecute()
 {
     // maintain $r0 semantics
-    cpuXC->setIntReg(ZeroReg, 0);
+    thread->setIntReg(ZeroReg, 0);
 #if THE_ISA == ALPHA_ISA
-    cpuXC->setFloatReg(ZeroReg, 0.0);
+    thread->setFloatReg(ZeroReg, 0.0);
 #endif // ALPHA_ISA
 
     // keep an instruction count
     numInst++;
     numInsts++;
 
-    cpuXC->func_exe_inst++;
+    thread->funcExeInst++;
 
     // check for instruction-count-based events
     comInstEventQueue[0]->serviceEvents(numInst);
 
     // decode the instruction
     inst = gtoh(inst);
-    curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC()));
+    curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC()));
 
     traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst,
-                                     cpuXC->readPC());
+                                     thread->readPC());
 
     DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
             curStaticInst->getName(), curStaticInst->getOpcode(),
             curStaticInst->machInst);
 
 #if FULL_SYSTEM
-    cpuXC->setInst(inst);
+    thread->setInst(inst);
 #endif // FULL_SYSTEM
 }
 
@@ -410,17 +410,17 @@ BaseSimpleCPU::postExecute()
 {
 #if FULL_SYSTEM
     if (system->kernelBinning->fnbin) {
-        assert(cpuXC->getKernelStats());
+        assert(thread->getKernelStats());
         system->kernelBinning->execute(tc, inst);
     }
 
-    if (cpuXC->profile) {
+    if (thread->profile) {
         bool usermode =
-            (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
-        cpuXC->profilePC = usermode ? 1 : cpuXC->readPC();
-        ProfileNode *node = cpuXC->profile->consume(tc, inst);
+            (thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+        thread->profilePC = usermode ? 1 : thread->readPC();
+        ProfileNode *node = thread->profile->consume(tc, inst);
         if (node)
-            cpuXC->profileNode = node;
+            thread->profileNode = node;
     }
 #endif
 
@@ -433,7 +433,7 @@ BaseSimpleCPU::postExecute()
         comLoadEventQueue[0]->serviceEvents(numLoad);
     }
 
-    traceFunctions(cpuXC->readPC());
+    traceFunctions(thread->readPC());
 
     if (traceData) {
         traceData->finalize();
@@ -448,17 +448,17 @@ BaseSimpleCPU::advancePC(Fault fault)
 #if FULL_SYSTEM
         fault->invoke(tc);
 #else // !FULL_SYSTEM
-        fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC());
+        fatal("fault (%s) detected @ PC %08p", fault->name(), thread->readPC());
 #endif // FULL_SYSTEM
     }
     else {
         // go to the next instruction
-        cpuXC->setPC(cpuXC->readNextPC());
+        thread->setPC(thread->readNextPC());
 #if THE_ISA == ALPHA_ISA
-        cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
+        thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
 #else
-        cpuXC->setNextPC(cpuXC->readNextNPC());
-        cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
+        thread->setNextPC(thread->readNextNPC());
+        thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
 #endif
 
     }
@@ -466,9 +466,9 @@ BaseSimpleCPU::advancePC(Fault fault)
 #if FULL_SYSTEM
     Addr oldpc;
     do {
-        oldpc = cpuXC->readPC();
+        oldpc = thread->readPC();
         system->pcEventQueue.service(tc);
-    } while (oldpc != cpuXC->readPC());
+    } while (oldpc != thread->readPC());
 #endif
 }