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authorSteve Reinhardt <steve.reinhardt@amd.com>2010-03-23 08:50:57 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2010-03-23 08:50:57 -0700
commit4d77ea7a5783d1de87a8eb804b17a6ef352998ce (patch)
treefbf1fd950e46885fdca93abbaf689f5131752995 /src/cpu/simple/base.cc
parentd484e1b334c6fd3f2721a2a4628c2324ed14fd08 (diff)
downloadgem5-4d77ea7a5783d1de87a8eb804b17a6ef352998ce.tar.xz
cpu: fix exec tracing memory corruption bug
Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. It turns out that there was never a need to access traceData after initiating the translation, as the traced data was always available earlier; this ordering was merely historical. Furthermore, traceData->setAddress() and traceData->setData() were being called both from the CPU model and the ISA definition, often redundantly. This patch standardizes all setAddress and setData calls for memory instructions to be in the CPU models and not in the ISA definition. It also moves those calls above the translation calls to eliminate the crashes.
Diffstat (limited to 'src/cpu/simple/base.cc')
-rw-r--r--src/cpu/simple/base.cc21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 0104e1b1f..17ba6a10b 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -205,6 +205,27 @@ change_thread_state(ThreadID tid, int activate, int priority)
{
}
+void
+BaseSimpleCPU::prefetch(Addr addr, unsigned flags)
+{
+ if (traceData) {
+ traceData->setAddr(addr);
+ }
+
+ // need to do this...
+}
+
+void
+BaseSimpleCPU::writeHint(Addr addr, int size, unsigned flags)
+{
+ if (traceData) {
+ traceData->setAddr(addr);
+ }
+
+ // need to do this...
+}
+
+
Fault
BaseSimpleCPU::copySrcTranslate(Addr src)
{