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authorAli Saidi <saidi@eecs.umich.edu>2007-06-01 14:16:58 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-06-01 14:16:58 -0400
commitd8f676996222dfc2d2666bdc88499c58f1c1246c (patch)
tree9915e206da02739e7773441c1e2a2a56221219d4 /src/cpu/simple/base.cc
parentd8c487c40112590b541dc1e74b435ecb8fe8cef8 (diff)
downloadgem5-d8f676996222dfc2d2666bdc88499c58f1c1246c.tar.xz
cast sizeof(MachInst) to Addr before generating a mask
--HG-- extra : convert_revision : 1ae34a069bbd997a8f888f69415fbeaaf4ade0b3
Diffstat (limited to 'src/cpu/simple/base.cc')
-rw-r--r--src/cpu/simple/base.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 5e078c502..da50a3eb0 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -329,7 +329,7 @@ BaseSimpleCPU::checkForInterrupts()
Fault
BaseSimpleCPU::setupFetchRequest(Request *req)
{
- uint64_t threadPC = thread->readPC();
+ Addr threadPC = thread->readPC();
// set up memory request for instruction fetch
#if ISA_HAS_DELAY_SLOT
@@ -340,9 +340,9 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
thread->readNextPC());
#endif
- const Addr PCMask = ~(sizeof(MachInst) - 1);
- Addr fetchPC = thread->readPC() + fetchOffset;
- req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, threadPC());
+ const Addr PCMask = ~((Addr)sizeof(MachInst) - 1);
+ Addr fetchPC = threadPC + fetchOffset;
+ req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, threadPC);
Fault fault = thread->translateInstReq(req);
@@ -380,7 +380,7 @@ BaseSimpleCPU::preExecute()
//This should go away once the constructor can be set up properly
predecoder.setTC(thread->getTC());
//If more fetch data is needed, pass it in.
- const Addr PCMask = ~(sizeof(MachInst) - 1);
+ const Addr PCMask = ~((Addr)sizeof(MachInst) - 1);
if(predecoder.needMoreBytes())
predecoder.moreBytes((thread->readPC() & PCMask) + fetchOffset,
0, inst);