diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-01 17:12:43 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-01 17:12:43 -0700 |
| commit | abe18be544014bee31d586bf8b26ab5b622b70b7 (patch) | |
| tree | ad4059302f30b79257cb50cb8e51c5da38c6418c /src/cpu/simple/base.cc | |
| parent | edeb8f39a7c3cbcf428743aca3017fa42865b04a (diff) | |
| parent | d8501ec17c590a0c6f5be92e121381667ca726b6 (diff) | |
| download | gem5-abe18be544014bee31d586bf8b26ab5b622b70b7.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision : 8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
Diffstat (limited to 'src/cpu/simple/base.cc')
| -rw-r--r-- | src/cpu/simple/base.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 801c96c88..22a210115 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -358,12 +358,12 @@ Fault BaseSimpleCPU::setupFetchRequest(Request *req) { // set up memory request for instruction fetch -#if THE_ISA == ALPHA_ISA - DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), - thread->readNextPC()); -#else +#if ISA_HAS_DELAY_SLOT DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), thread->readNextPC(),thread->readNextNPC()); +#else + DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), + thread->readNextPC()); #endif req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), @@ -450,12 +450,12 @@ BaseSimpleCPU::advancePC(Fault fault) else { // go to the next instruction thread->setPC(thread->readNextPC()); -#if THE_ISA == ALPHA_ISA - thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); -#else +#if ISA_HAS_DELAY_SLOT thread->setNextPC(thread->readNextNPC()); thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); assert(thread->readNextPC() != thread->readNextNPC()); +#else + thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); #endif } |