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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:25:42 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:25:42 -0700 |
| commit | e056e49c4562108eeb7abbbeb1ee8acb096fe363 (patch) | |
| tree | 162b440d59f688da34667ecf1add53bb4d52baf7 /src/cpu/simple/base.cc | |
| parent | 537239b278f7b8171d2eb09ef7f99c332266c48f (diff) | |
| download | gem5-e056e49c4562108eeb7abbbeb1ee8acb096fe363.tar.xz | |
Simple CPU: Make sure only instructions which complete without faulting are counted.
--HG--
extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
Diffstat (limited to 'src/cpu/simple/base.cc')
| -rw-r--r-- | src/cpu/simple/base.cc | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index aabaf1971..d6b124efc 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -357,12 +357,6 @@ BaseSimpleCPU::preExecute() thread->setFloatReg(ZeroReg, 0.0); #endif // ALPHA_ISA - // keep an instruction count - numInst++; - numInsts++; - - thread->funcExeInst++; - // check for instruction-count-based events comInstEventQueue[0]->serviceEvents(numInst); |