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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-14 03:53:51 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-14 03:53:51 -0500 |
| commit | 481eb6ae8018d0478c23fda7c5f9f3fa4db8de89 (patch) | |
| tree | e9b449bc6a2e7b15255c7a3c2d5984e0a99b452c /src/cpu/simple/base.cc | |
| parent | 9ffe0e7ba67ee194db885b96a7ed3630aed03584 (diff) | |
| download | gem5-481eb6ae8018d0478c23fda7c5f9f3fa4db8de89.tar.xz | |
arm: Fixes based on UBSan and static analysis
Another churn to clean up undefined behaviour, mostly ARM, but some
parts also touching the generic part of the code base.
Most of the fixes are simply ensuring that proper intialisation. One
of the more subtle changes is the return type of the sign-extension,
which is changed to uint64_t. This is to avoid shifting negative
values (undefined behaviour) in the ISA code.
Diffstat (limited to 'src/cpu/simple/base.cc')
| -rw-r--r-- | src/cpu/simple/base.cc | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 636e08899..9cfbd5f93 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -88,7 +88,8 @@ using namespace TheISA; BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) : BaseCPU(p), branchPred(p->branchPred), - traceData(NULL), thread(NULL) + traceData(NULL), thread(NULL), _status(Idle), interval_stats(false), + inst() { if (FullSystem) thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb, @@ -266,18 +267,6 @@ BaseSimpleCPU::regStats() .prereq(dcacheStallCycles) ; - icacheRetryCycles - .name(name() + ".icache_retry_cycles") - .desc("ICache total retry cycles") - .prereq(icacheRetryCycles) - ; - - dcacheRetryCycles - .name(name() + ".dcache_retry_cycles") - .desc("DCache total retry cycles") - .prereq(dcacheRetryCycles) - ; - statExecutedInstType .init(Enums::Num_OpClass) .name(name() + ".op_class") |