arch, cpu: Factor out the ExecContext into a proper base class

We currently generate and compile one version of the ISA code per CPU
model. This is obviously wasting a lot of resources at compile
time. This changeset factors out the interface into a separate
ExecContext class, which also serves as documentation for the
interface between CPUs and the ISA code. While doing so, this
changeset also fixes up interface inconsistencies between the
different CPU models.

The main argument for using one set of ISA code per CPU model has
always been performance as this avoid indirect branches in the
generated code. However, this argument does not hold water. Booting
Linux on a simulated ARM system running in atomic mode
(opt/10.linux-boot/realview-simple-atomic) is actually 2% faster
(compiled using clang 3.4) after applying this patch. Additionally,
compilation time is decreased by 35%.

1 files changed, 15 insertions, 15 deletions

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 47034c300..3755a94a9 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -50,6 +50,7 @@
 #include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
+#include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
@@ -79,7 +80,7 @@ namespace Trace {
 struct BaseSimpleCPUParams;
 class BPredUnit;
 
-class BaseSimpleCPU : public BaseCPU
+class BaseSimpleCPU : public BaseCPU, public ExecContext
 {
   protected:
     typedef TheISA::MiscReg MiscReg;
@@ -293,8 +294,7 @@ class BaseSimpleCPU : public BaseCPU
     // These functions are only used in CPU models that split
     // effective address computation from the actual memory access.
     void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
-    Addr getEA()        { panic("BaseSimpleCPU::getEA() not implemented\n");
-        M5_DUMMY_RETURN}
+    Addr getEA() const  { panic("BaseSimpleCPU::getEA() not implemented\n"); }
 
     // The register accessor methods provide the index of the
     // instruction's operand (e.g., 0 or 1), not the architectural
@@ -307,7 +307,7 @@ class BaseSimpleCPU : public BaseCPU
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntRegOperand(const StaticInst *si, int idx)
+    IntReg readIntRegOperand(const StaticInst *si, int idx)
     {
         numIntRegReads++;
         return thread->readIntReg(si->srcRegIdx(idx));
@@ -334,7 +334,7 @@ class BaseSimpleCPU : public BaseCPU
         return thread->readCCReg(reg_idx);
     }
 
-    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
+    void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
     {
         numIntRegWrites++;
         thread->setIntReg(si->destRegIdx(idx), val);
@@ -370,7 +370,7 @@ class BaseSimpleCPU : public BaseCPU
             traceData->setPredicate(val);
         }
     }
-    TheISA::PCState pcState() { return thread->pcState(); }
+    TheISA::PCState pcState() const { return thread->pcState(); }
     void pcState(const TheISA::PCState &val) { thread->pcState(val); }
     Addr instAddr() { return thread->instAddr(); }
     Addr nextInstAddr() { return thread->nextInstAddr(); }
@@ -423,26 +423,26 @@ class BaseSimpleCPU : public BaseCPU
         thread->demapDataPage(vaddr, asn);
     }
 
-    unsigned readStCondFailures() {
+    unsigned int readStCondFailures() const {
         return thread->readStCondFailures();
     }
 
-    void setStCondFailures(unsigned sc_failures) {
+    void setStCondFailures(unsigned int sc_failures) {
         thread->setStCondFailures(sc_failures);
     }
 
-     MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
-     {
+    MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
+    {
         panic("Simple CPU models do not support multithreaded "
               "register access.\n");
-     }
+    }
 
-     void setRegOtherThread(int regIdx, const MiscReg &val,
-                            ThreadID tid = InvalidThreadID)
-     {
+    void setRegOtherThread(int regIdx, MiscReg val,
+                           ThreadID tid = InvalidThreadID)
+    {
         panic("Simple CPU models do not support multithreaded "
               "register access.\n");
-     }
+    }
 
     //Fault CacheOp(uint8_t Op, Addr EA);