summaryrefslogtreecommitdiff
path: root/src/cpu/simple/base.hh
diff options
context:
space:
mode:
authorAli Saidi <saidi@eecs.umich.edu>2007-03-07 15:04:44 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-03-07 15:04:44 -0500
commit49527ab55312bf02dfce20c45db8f173b0c2324e (patch)
treeb9212b195a7b253940aaaab5c8b9ef27e43d026e /src/cpu/simple/base.hh
parentea7bdf9f60c404761dfc568d5291c75747a2dd88 (diff)
parent689cab36c90b56b3c8a7cda16d758acdd89f9de1 (diff)
downloadgem5-49527ab55312bf02dfce20c45db8f173b0c2324e.tar.xz
Merge zizzer:/bk/newmem
into zeep.pool:/tmp/newmem --HG-- extra : convert_revision : f078a05729b5fe464a06a58bc4adcb374f560572
Diffstat (limited to 'src/cpu/simple/base.hh')
-rw-r--r--src/cpu/simple/base.hh22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 01c8e8eb7..980ea2f96 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -284,14 +284,19 @@ class BaseSimpleCPU : public BaseCPU
void setNextPC(uint64_t val) { thread->setNextPC(val); }
void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
+ MiscReg readMiscRegNoEffect(int misc_reg)
+ {
+ return thread->readMiscRegNoEffect(misc_reg);
+ }
+
MiscReg readMiscReg(int misc_reg)
{
return thread->readMiscReg(misc_reg);
}
- MiscReg readMiscRegWithEffect(int misc_reg)
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
- return thread->readMiscRegWithEffect(misc_reg);
+ return thread->setMiscRegNoEffect(misc_reg, val);
}
void setMiscReg(int misc_reg, const MiscReg &val)
@@ -299,34 +304,29 @@ class BaseSimpleCPU : public BaseCPU
return thread->setMiscReg(misc_reg, val);
}
- void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
- {
- return thread->setMiscRegWithEffect(misc_reg, val);
- }
-
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
- return thread->readMiscReg(reg_idx);
+ return thread->readMiscRegNoEffect(reg_idx);
}
MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
- return thread->readMiscRegWithEffect(reg_idx);
+ return thread->readMiscReg(reg_idx);
}
void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
- return thread->setMiscReg(reg_idx, val);
+ return thread->setMiscRegNoEffect(reg_idx, val);
}
void setMiscRegOperandWithEffect(
const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
- return thread->setMiscRegWithEffect(reg_idx, val);
+ return thread->setMiscReg(reg_idx, val);
}
unsigned readStCondFailures() {