CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5

Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU.  These changes have only been tested with the ARM ISA.  Other
ISAs potentially require modification.

1 files changed, 21 insertions, 0 deletions

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index ad281aa2b..56e5e5608 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -37,6 +49,7 @@
 #include "base/statistics.hh"
 #include "config/full_system.hh"
 #include "config/the_isa.hh"
+#include "config/use_checker.hh"
 #include "cpu/base.hh"
 #include "cpu/decode.hh"
 #include "cpu/pc_event.hh"
@@ -48,6 +61,10 @@
 #include "sim/eventq.hh"
 #include "sim/system.hh"
 
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif
+
 // forward declarations
 #if FULL_SYSTEM
 class Processor;
@@ -120,6 +137,10 @@ class BaseSimpleCPU : public BaseCPU
      * objects to modify this thread's state.
      */
     ThreadContext *tc;
+
+#if USE_CHECKER
+    CheckerCPU *checker;
+#endif
   protected:
 
     enum Status {