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author | Joel Hestness <hestness@cs.utexas.edu> | 2011-02-06 22:14:17 -0800 |
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committer | Joel Hestness <hestness@cs.utexas.edu> | 2011-02-06 22:14:17 -0800 |
commit | b4c10bd6800b5ab5adee3035f1908d7a49a14ca9 (patch) | |
tree | d21b1bbf5c8df8c77d77b6983779b24189a1d8cb /src/cpu/simple/base.hh | |
parent | a679e732cee821616c20cc13c22ad2877072ff14 (diff) | |
download | gem5-b4c10bd6800b5ab5adee3035f1908d7a49a14ca9.tar.xz |
mcpat: Adds McPAT performance counters
Updated patches from Rick Strong's set that modify performance counters for
McPAT
Diffstat (limited to 'src/cpu/simple/base.hh')
-rw-r--r-- | src/cpu/simple/base.hh | 46 |
1 files changed, 45 insertions, 1 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index bd967b185..628432d76 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -182,7 +182,7 @@ class BaseSimpleCPU : public BaseCPU { numInst++; numInsts++; - + system->totalNumInsts++; thread->funcExeInst++; } @@ -191,8 +191,42 @@ class BaseSimpleCPU : public BaseCPU return numInst - startNumInst; } + //number of integer alu accesses + Stats::Scalar numIntAluAccesses; + + //number of float alu accesses + Stats::Scalar numFpAluAccesses; + + //number of function calls/returns + Stats::Scalar numCallsReturns; + + //conditional control instructions; + Stats::Scalar numCondCtrlInsts; + + //number of int instructions + Stats::Scalar numIntInsts; + + //number of float instructions + Stats::Scalar numFpInsts; + + //number of integer register file accesses + Stats::Scalar numIntRegReads; + Stats::Scalar numIntRegWrites; + + //number of float register file accesses + Stats::Scalar numFpRegReads; + Stats::Scalar numFpRegWrites; + // number of simulated memory references Stats::Scalar numMemRefs; + Stats::Scalar numLoadInsts; + Stats::Scalar numStoreInsts; + + // number of idle cycles + Stats::Formula numIdleCycles; + + // number of busy cycles + Stats::Formula numBusyCycles; // number of simulated loads Counter numLoad; @@ -240,28 +274,33 @@ class BaseSimpleCPU : public BaseCPU uint64_t readIntRegOperand(const StaticInst *si, int idx) { + numIntRegReads++; return thread->readIntReg(si->srcRegIdx(idx)); } FloatReg readFloatRegOperand(const StaticInst *si, int idx) { + numFpRegReads++; int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatReg(reg_idx); } FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { + numFpRegReads++; int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatRegBits(reg_idx); } void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { + numIntRegWrites++; thread->setIntReg(si->destRegIdx(idx), val); } void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { + numFpRegWrites++; int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; thread->setFloatReg(reg_idx, val); } @@ -269,6 +308,7 @@ class BaseSimpleCPU : public BaseCPU void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { + numFpRegWrites++; int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; thread->setFloatRegBits(reg_idx, val); } @@ -294,16 +334,19 @@ class BaseSimpleCPU : public BaseCPU MiscReg readMiscReg(int misc_reg) { + numIntRegReads++; return thread->readMiscReg(misc_reg); } void setMiscReg(int misc_reg, const MiscReg &val) { + numIntRegWrites++; return thread->setMiscReg(misc_reg, val); } MiscReg readMiscRegOperand(const StaticInst *si, int idx) { + numIntRegReads++; int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; return thread->readMiscReg(reg_idx); } @@ -311,6 +354,7 @@ class BaseSimpleCPU : public BaseCPU void setMiscRegOperand( const StaticInst *si, int idx, const MiscReg &val) { + numIntRegWrites++; int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; return thread->setMiscReg(reg_idx, val); } |