cpu: simple: Add support for using branch predictors

This changesets adds branch predictor support to the
BaseSimpleCPU. The simple CPUs normally don't need a branch predictor,
however, there are at least two cases where it can be desirable:

  1) A simple CPU can be used to warm the branch predictor of an O3
     CPU before switching to the slower O3 model.

  2) The simple CPU can be used as a quick way of evaluating/debugging
     new branch predictors since it exposes branch predictor
     statistics.

Limitations:
  * Since the simple CPU doesn't speculate, only one instruction will
    be active in the branch predictor at a time (i.e., the branch
    predictor will never see speculative branches).

  * The outcome of a branch prediction does not affect the performance
    of the simple CPU.

1 files changed, 15 insertions, 1 deletions

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 8134465af..ad672da6c 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -77,7 +77,7 @@ namespace Trace {
 }
 
 struct BaseSimpleCPUParams;
-
+class BPredUnit;
 
 class BaseSimpleCPU : public BaseCPU
 {
@@ -87,6 +87,8 @@ class BaseSimpleCPU : public BaseCPU
     typedef TheISA::FloatRegBits FloatRegBits;
     typedef TheISA::CCReg CCReg;
 
+    BPredUnit *branchPred;
+
   protected:
     Trace::InstRecord *traceData;
 
@@ -272,6 +274,15 @@ class BaseSimpleCPU : public BaseCPU
     Stats::Scalar dcacheRetryCycles;
     Counter lastDcacheRetry;
 
+    /// @{
+    /// Total number of branches fetched
+    Stats::Scalar numBranches;
+    /// Number of branches predicted as taken
+    Stats::Scalar numPredictedBranches;
+    /// Number of misprediced branches
+    Stats::Scalar numBranchMispred;
+    /// @}
+
     void serializeThread(std::ostream &os, ThreadID tid);
     void unserializeThread(Checkpoint *cp, const std::string &section,
                            ThreadID tid);
@@ -446,6 +457,9 @@ class BaseSimpleCPU : public BaseCPU
 
     bool misspeculating() { return thread->misspeculating(); }
     ThreadContext *tcBase() { return tc; }
+
+  private:
+    TheISA::PCState pred_pc;
 };
 
 #endif // __CPU_SIMPLE_BASE_HH__