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authorSteve Reinhardt <steve.reinhardt@amd.com>2013-10-15 14:22:43 -0400
committerSteve Reinhardt <steve.reinhardt@amd.com>2013-10-15 14:22:43 -0400
commit219c423f1fb0f9a559bfa87f9812426d5e2c3e29 (patch)
tree7980ae867c4642e710af7cd5d0ad7fe51c0b6687 /src/cpu/simple/base.hh
parenta830e63de71e5929b8ff8e334bc872faa9193a8b (diff)
downloadgem5-219c423f1fb0f9a559bfa87f9812426d5e2c3e29.tar.xz
cpu: rename *_DepTag constants to *_Reg_Base
Make these names more meaningful. Specifically, made these substitutions: s/FP_Base_DepTag/FP_Reg_Base/g; s/Ctrl_Base_DepTag/Misc_Reg_Base/g; s/Max_DepTag/Max_Reg_Index/g;
Diffstat (limited to 'src/cpu/simple/base.hh')
-rw-r--r--src/cpu/simple/base.hh12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 7e84dcc16..f2e1b278a 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -296,14 +296,14 @@ class BaseSimpleCPU : public BaseCPU
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
numFpRegReads++;
- int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
return thread->readFloatReg(reg_idx);
}
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
numFpRegReads++;
- int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
return thread->readFloatRegBits(reg_idx);
}
@@ -316,7 +316,7 @@ class BaseSimpleCPU : public BaseCPU
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
numFpRegWrites++;
- int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatReg(reg_idx, val);
}
@@ -324,7 +324,7 @@ class BaseSimpleCPU : public BaseCPU
FloatRegBits val)
{
numFpRegWrites++;
- int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatRegBits(reg_idx, val);
}
@@ -362,7 +362,7 @@ class BaseSimpleCPU : public BaseCPU
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
numIntRegReads++;
- int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+ int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
return thread->readMiscReg(reg_idx);
}
@@ -370,7 +370,7 @@ class BaseSimpleCPU : public BaseCPU
const StaticInst *si, int idx, const MiscReg &val)
{
numIntRegWrites++;
- int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
+ int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
return thread->setMiscReg(reg_idx, val);
}