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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:31 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 15:04:31 -0500 |
commit | 689cab36c90b56b3c8a7cda16d758acdd89f9de1 (patch) | |
tree | 2f0115320e0a6cfd13e5b054baa0ca13d5655519 /src/cpu/simple/base.hh | |
parent | 329db76e47c825d4ecbe0f5251dbcfaf2ec09516 (diff) | |
download | gem5-689cab36c90b56b3c8a7cda16d758acdd89f9de1.tar.xz |
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
--HG--
extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
Diffstat (limited to 'src/cpu/simple/base.hh')
-rw-r--r-- | src/cpu/simple/base.hh | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 01c8e8eb7..980ea2f96 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -284,14 +284,19 @@ class BaseSimpleCPU : public BaseCPU void setNextPC(uint64_t val) { thread->setNextPC(val); } void setNextNPC(uint64_t val) { thread->setNextNPC(val); } + MiscReg readMiscRegNoEffect(int misc_reg) + { + return thread->readMiscRegNoEffect(misc_reg); + } + MiscReg readMiscReg(int misc_reg) { return thread->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg) + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) { - return thread->readMiscRegWithEffect(misc_reg); + return thread->setMiscRegNoEffect(misc_reg, val); } void setMiscReg(int misc_reg, const MiscReg &val) @@ -299,34 +304,29 @@ class BaseSimpleCPU : public BaseCPU return thread->setMiscReg(misc_reg, val); } - void setMiscRegWithEffect(int misc_reg, const MiscReg &val) - { - return thread->setMiscRegWithEffect(misc_reg, val); - } - MiscReg readMiscRegOperand(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->readMiscReg(reg_idx); + return thread->readMiscRegNoEffect(reg_idx); } MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->readMiscRegWithEffect(reg_idx); + return thread->readMiscReg(reg_idx); } void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val) { int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->setMiscReg(reg_idx, val); + return thread->setMiscRegNoEffect(reg_idx, val); } void setMiscRegOperandWithEffect( const StaticInst *si, int idx, const MiscReg &val) { int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->setMiscRegWithEffect(reg_idx, val); + return thread->setMiscReg(reg_idx, val); } unsigned readStCondFailures() { |