summaryrefslogtreecommitdiff
path: root/src/cpu/simple/base.hh
diff options
context:
space:
mode:
authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-01-07 13:05:52 -0500
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-01-07 13:05:52 -0500
commit009970f59b86eac6c9a35eeb175dd9e3a3079d13 (patch)
tree03119f68fd1e03ff753954b63722b916b39f6737 /src/cpu/simple/base.hh
parent5fb00e1df6b2b7d9db472d0c25765263ed1b839f (diff)
downloadgem5-009970f59b86eac6c9a35eeb175dd9e3a3079d13.tar.xz
cpu: Unify the serialization code for all of the CPU models
Cleanup the serialization code for the simple CPUs and the O3 CPU. The CPU-specific code has been replaced with a (un)serializeThread that serializes the thread state / context of a specific thread. Assuming that the thread state class uses the CPU-specific thread state uses the base thread state serialization code, this allows us to restore a checkpoint with any of the CPU models.
Diffstat (limited to 'src/cpu/simple/base.hh')
-rw-r--r--src/cpu/simple/base.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 9bf144326..18b97c42f 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -137,7 +137,6 @@ class BaseSimpleCPU : public BaseCPU
DcacheRetry,
DcacheWaitResponse,
DcacheWaitSwitch,
- SwitchedOut
};
Status _status;
@@ -265,8 +264,9 @@ class BaseSimpleCPU : public BaseCPU
Stats::Scalar dcacheRetryCycles;
Counter lastDcacheRetry;
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string &section);
+ void serializeThread(std::ostream &os, ThreadID tid);
+ void unserializeThread(Checkpoint *cp, const std::string &section,
+ ThreadID tid);
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.