cpu: use probes infrastructure to do simpoint profiling

Instead of having code embedded in cpu model to do simpoint profiling use
the probes infrastructure to do it.

1 files changed, 119 insertions, 0 deletions

diff --git a/src/cpu/simple/probes/simpoint.hh b/src/cpu/simple/probes/simpoint.hh
new file mode 100644
index 000000000..e2c343755
--- /dev/null
+++ b/src/cpu/simple/probes/simpoint.hh
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2012-2014 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Dam Sunwoo
+ *          Curtis Dunham
+ */
+
+#ifndef __CPU_SIMPLE_PROBES_SIMPOINT_HH__
+#define __CPU_SIMPLE_PROBES_SIMPOINT_HH__
+
+#include "base/hashmap.hh"
+#include "cpu/simple_thread.hh"
+#include "params/SimPoint.hh"
+#include "sim/probe/probe.hh"
+
+/**
+ * Probe for SimPoints BBV generation
+ */
+
+/**
+ *  Start and end address of basic block for SimPoint profiling.
+ *  This structure is used to look up the hash table of BBVs.
+ *  - first: PC of first inst in basic block
+ *  - second: PC of last inst in basic block
+ */
+typedef std::pair<Addr, Addr> BasicBlockRange;
+
+/** Overload hash function for BasicBlockRange type */
+__hash_namespace_begin
+template <>
+struct hash<BasicBlockRange>
+{
+  public:
+    size_t operator()(const BasicBlockRange &bb) const {
+        return hash<Addr>()(bb.first + bb.second);
+    }
+};
+__hash_namespace_end
+
+class SimPoint : public ProbeListenerObject
+{
+  public:
+    SimPoint(const SimPointParams *params);
+    virtual ~SimPoint();
+
+    virtual void init();
+
+    virtual void regProbeListeners();
+
+    /**
+     * Profile basic blocks for SimPoints.
+     * Called at every macro inst to increment basic block inst counts and
+     * to profile block if end of block.
+     */
+    void profile(const std::pair<SimpleThread*, StaticInstPtr>&);
+
+  private:
+    /** SimPoint profiling interval size in instructions */
+    const uint64_t intervalSize;
+
+    /** Inst count in current basic block */
+    uint64_t intervalCount;
+    /** Excess inst count from previous interval*/
+    uint64_t intervalDrift;
+    /** Pointer to SimPoint BBV output stream */
+    std::ostream *simpointStream;
+
+    /** Basic Block information */
+    struct BBInfo {
+        /** Unique ID */
+        uint64_t id;
+        /** Num of static insts in BB */
+        uint64_t insts;
+        /** Accumulated dynamic inst count executed by BB */
+        uint64_t count;
+    };
+
+    /** Hash table containing all previously seen basic blocks */
+    m5::hash_map<BasicBlockRange, BBInfo> bbMap;
+    /** Currently executing basic block */
+    BasicBlockRange currentBBV;
+    /** inst count in current basic block */
+    uint64_t currentBBVInstCount;
+};
+
+#endif // __CPU_SIMPLE_PROBES_SIMPOINT_HH__