CPU: Fix bug when a split transaction is issued to a faster cache

In the case of a split transaction and a cache that is faster than a CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.

1 files changed, 10 insertions, 1 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2abe9cd59..7307f2fc9 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -999,7 +999,16 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
         if (next_tick == curTick) {
             cpu->completeDataAccess(pkt);
         } else {
-            tickEvent.schedule(pkt, next_tick);
+            if (!tickEvent.scheduled()) {
+                tickEvent.schedule(pkt, next_tick);
+            } else {
+                // In the case of a split transaction and a cache that is
+                // faster than a CPU we could get two responses before
+                // next_tick expires
+                if (!retryEvent.scheduled())
+                    schedule(retryEvent, next_tick);
+                return false;
+            }
         }
 
         return true;