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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-31 02:08:44 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-31 02:08:44 -0500 |
| commit | 4862879a9420c52d48532d957b616c458b643a1e (patch) | |
| tree | 576a3c724920ede579d5f9fe7ec52e41911a306a /src/cpu/simple/timing.cc | |
| parent | 79d4bede429bb5c3413fcd0cfe6f2d1790c8312d (diff) | |
| download | gem5-4862879a9420c52d48532d957b616c458b643a1e.tar.xz | |
Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names.
--HG--
extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index fe6775ea4..438417882 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -665,8 +665,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) Param<int> cpu_id; #if FULL_SYSTEM - SimObjectParam<AlphaITB *> itb; - SimObjectParam<AlphaDTB *> dtb; + SimObjectParam<TheISA::ITB *> itb; + SimObjectParam<TheISA::DTB *> dtb; Param<Tick> profile; #else SimObjectParam<Process *> workload; |